@article{Galupa_2016, title={Logic Circuits Timing Analysis Using Timed Logic Variables}, volume={12}, url={https://eujournal.org/index.php/esj/article/view/7598}, DOI={10.19044/esj.2016.v12n18p35}, abstractNote={Combinational logic circuit timing analysis is an important issue that all designers need to address. The present paper presents a simple and compact analysis procedure. We follow the guidelines drawn by previous methods, but we shall define new time-dependent logic variables that help us improve their efficiency. By using the methodology suggested, we shall replace a very laborious technique (pure delay circuit + time constants method) with a simpler procedure that can pinpoint the specific conditions for a logic circuit’s anomalous behaviour within a few simple steps. Considering the logic function implemented the methodology presented will require analysis of only a limited number of situations/combinations to determine the presence of an anomalous behaviour. When anomalous behaviour is identified, the methodology provides a clear timing description.}, number={18}, journal={European Scientific Journal, ESJ}, author={Galupa, Nicolae}, year={2016}, month={Jun.}, pages={35} }