AN ALGORITHM FOR FAULT TOLERANCE IN FPGA - R.V. Kshirsagar; Sanjeev Sharma (European Scientific Journal, ESJ, 2013)
﻿﻿﻿Modern Field Programmable Gate Arrays (FPGAs) posses small feature sizes, and have gained popularity. However, FPGA can suffer from faults due to the small feature sizes and harsh external conditions that are faced by a mission-critical system. Therefore, the architecture of FPGA must be tested to ensure a reliable system performance. At the same time, the test process should be non-intrusive, i.e., applications and FPGA regions that are not being tested remain unaffected. A fault tolerance methodology is, therefore, required that not only verifies the reliability of FPGA architecture, but also does not degrade the performance of other, running FPGA applications. The homogeneous structure of Field programmable gate arrays (FPGAs) suggests that the defect tolerance can be achieved by shifting the configuration data inside the FPGA. In this paper we have suggested one such fault tolerance approach through the proposed shifting allocation method.