PERFORMANCE ANALYSES OF SPECULATIVE VIRTUAL CHANNEL ROUTER FOR NETWORK-ON-CHIP - Amit Kumar Lamba; Bharati B. Sayankar; Pankaj Agrawal (European Scientific Journal, ESJ, 2014)
Network -On-Chip (NoC) is becoming the backbone of System on chip (SoC) architecture and router is the heart of an NOC architecture. This paper explores two types of Routers. First is the Speculative Virtual Channel Router for Network-On-Chip (NoC) and second, non- speculative Virtual Channel Router for Network-On-Chip (NoC). In the speculative Virtual channel router, Speculative virtual channel allocation and the speculative switch allocation takes place at the same time on the other hand in non-speculative virtual channel route channel allocation and switch allocation takes place serially. Major components of proposed routers are Input Port, Allocators and the contention free crossbar switch. Performance analysis on two parameters, Area and Delay for both types of design is presented with the help of “Xilinx ISE-13.1” design suite.